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2000, vol.100, no.295	2000, vol.100, no.296	2000, vol.100, no.373	2000, vol.100, no.374	2000, vol.100, no.477	2000, vol.100, no.517
2000, vol.100, no.603	2000, vol.100, no.652	2000, vol.100, no.653	2000, vol.100, no.668

题名	作者	出版年	年卷期
Three-dimensional capacitance analysis of an SRAM cell	Yoshiaki Takemura; Ken-ichi Osada; Masayoshi Yagyu; Ken Yamaguchi; Jiro Ushio; Takuya Maruizumi	2000	2000, vol.100, no.295
Characterization of interconnect coupling noise using in-situ delay-change curve measurements	Takashi Sato; Yu Cao; Dennis Sylvester; Chenming Hu	2000	2000, vol.100, no.295
New method of extracting inductance from VLSI circuit and simulation with this method	Y. Nakashima; M. Ikeda; K. Asada	2000	2000, vol.100, no.295
Clock tree synthesis for shrinking a chip design	Inoue, Hiroaki; Masato Edahiro	2000	2000, vol.100, no.295
A more accurate skew model for well-balanced	Xiaohong Jiang; Susumu Horiguchi	2000	2000, vol.100, no.295
A system generating SPICE parameters to estimated fluctuation of circuit performance	Makoto Kidera; Motoaki Tanizawa; Kenichiro Sonoda; Kiyoshi Ishikawa; Norihiko Kotani; Masahide Inuishi	2000	2000, vol.100, no.295
A method of worst-case analysis for process fluctuation induced circuit characteristics variations	Tetsuya Yamaguchi	2000	2000, vol.100, no.295
Recognition of layout by parametric BSG for reuse of layout design	Zhonglin Wu; Keishi Sakanushi; Yoji Kajitani	2000	2000, vol.100, no.295
A floorplan method based on the boundary method and genetic algorithm	Jin Takahashi; Akinori Kanasugi; Kenji Ohshima	2000	2000, vol.100, no.295