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期刊
ISSN
1751-8601
刊名
IET Computers & Digital Techniques
参考译名
IET计算机与数字技术
收藏年代
2007~2012
关联期刊
参考译名
收藏年代
IEE Proceedings
英国电气工程师学会论文集:计算机与数字技术
1999~2006
全部
2007
2008
2009
2010
2011
2012
2012, vol.6, no.1
2012, vol.6, no.2
2012, vol.6, no.3
2012, vol.6, no.4
2012, vol.6, no.5
2012, vol.6, no.6
题名
作者
出版年
年卷期
Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits
G. Jaberipur; B. Parhami
2012
2012, vol.6, no.5
Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2~n-1, 2~n, 2~n+1}
S. Timarchi; M. Fazlali
2012
2012, vol.6, no.5
Decimal floating-point antilogarithmic converter based on selection by rounding: algorithm and architecture
D. Chen; L. Han; S. B. Ko
2012
2012, vol.6, no.5
Massively parallel modular exponentiation method and its implementation in software and hardware for high-performance cryptographic systems
N. Nedjah; L. M. Mourelle; M. Santana; S. Raposo
2012
2012, vol.6, no.5
Supporting non-contiguous processor allocation in mesh-based chip multiprocessors using virtual point-to-point links
M. Asadinia; M. Modarressi; H. Sarbazi-azad
2012
2012, vol.6, no.5
Application-specific topology generation algorithms for network-on-chip design
S. Tosun; Y. Ar; S. Ozdemir
2012
2012, vol.6, no.5
Advanced architecture optimisation and performance analysis of a reconfigurable grid ALU processor
S. Uhrig; R. Jahr; T. Ungerer
2012
2012, vol.6, no.5
Throughput enhancement for repetitive internal cores in latency-insensitive systems
M. Zare; S. Hessabi; M. Goudarzi
2012
2012, vol.6, no.5
Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits
G. Jaberipur; B. Parhami
2012
2012, vol.6, no.5
Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2~n-1, 2~n, 2~n+1}
S. Timarchi; M. Fazlali
2012
2012, vol.6, no.5
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