期刊


ISSN0925-1030
刊名Analog Integrated Circuits and Signal Processing
参考译名模拟集成电路与信号处理
收藏年代2000～2024



全部

2000 2001 2002 2003 2004 2005
2006 2007 2008 2009 2010 2011
2012 2013 2014 2015 2016 2017
2018 2019 2020 2021 2022 2023
2024

2021, vol.106, no.1 2021, vol.106, no.2 2021, vol.106, no.3 2021, vol.107, no.1 2021, vol.107, no.2 2021, vol.107, no.3
2021, vol.108, no.1 2021, vol.108, no.2 2021, vol.108, no.3 2021, vol.109, no.1 2021, vol.109, no.2 2021, vol.109, no.3

题名作者出版年年卷期
Design analysis of GOS-HEFET on lower Subthreshold Swing SOISatyanarayana, B. V. V.; Prakash, M. Durga20212021, vol.109, no.3
Design and verification of a high performance analog switch circuitZhang, Lin; Li, Jieyu; Wang, Yang; Hao, Jianxiu; Jin, Xiangliang; Peng, Yan; Luo, Jun20212021, vol.109, no.3
A 223-mu W single-to-differential RF mixer with 8.6dBm IIP3 using current-bleeding and body-effect for sub-6 GHz 5G applicationsGladson, S. Chrisben; Prasad, P. Siva; Manickam, Bhaskar20212021, vol.109, no.3
A 12-bit 10-MS/s SAR ADC with a weighted sampling time technique applied to C-DACShim, Min-Soo; Kang, Min-Seung; Lee, Jongwhan; Yoon, Kwang20212021, vol.109, no.3
Moving average filter for spur reduction in subsampling fractional PLLsBiswas, Debdut20212021, vol.109, no.3
Using nano-scale QCA technology for designing fault-tolerant 2:1 multiplexerWu, Linli; Shen, Zhangyi; Ji, Yun20212021, vol.109, no.3
Process evaluation in FinFET based 7T SRAM cellKumar, T. Santosh; Tripathi, Suman Lata20212021, vol.109, no.3
Phase locked loop-based clock synthesizer for reconfigurable analog-to-digital convertersCastro, Mateus B.; Souza, Raphael R. N.; Junior, Agord M. P.; Manera, Leandro T.; Lima, Eduardo R.20212021, vol.109, no.3
A new design of fault-tolerant digital comparator based on quantum-dot cellular automataJi, Yun20212021, vol.109, no.3
Design of bandpass-bandpass diplexers using rectangular-, T-, and L-shaped resonators for hybrid power amplifier and 5G applicationsTahmasbi, Meisam; Razaghian, Farhad; Roshani, Sobhan20212021, vol.109, no.3
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