期刊


ISSN0018-9219
刊名Proceedings of the IEEE
参考译名电气与电子工程师学会会报
收藏年代1998～2013



全部

1998 1999 2000 2001 2002 2003
2004 2005 2006 2007 2008 2009
2010 2011 2012 2013

2009, vol.97, no.1 2009, vol.97, no.10 2009, vol.97, no.11 2009, vol.97, no.12 2009, vol.97, no.2 2009, vol.97, no.3
2009, vol.97, no.4 2009, vol.97, no.5 2009, vol.97, no.6 2009, vol.97, no.7 2009, vol.97, no.8 2009, vol.97, no.9

题名作者出版年年卷期
SoC and SiP, the Yin and Yang of the Tao for the New Electronic EraALFONSO MAURELLI; DIDIER BELOT; GIOVANNI CAMPARDO20092009, vol.97, no.1
3-D Hyperintegration and Packaging Technologies for Micro-Nano SystemsJIAN-QIANG LU20092009, vol.97, no.1
3-D Stacked Package Technology and TrendsFLYNN P. CARSON; YOUNG CHEOL KIM; IN SANG YOON20092009, vol.97, no.1
Through-Silicon Via (TSV)MAKOTO MOTOYOSHI20092009, vol.97, no.1
High-Density Through Silicon Vias for 3-D LSIsMITSUMASA KOYANAGI; TAKAFUMI FUKUSHIMA; TETSU TANAKA20092009, vol.97, no.1
System on Wafer: A New Silicon Concept in SiPGILLES POUPON; NICOLAS SILLON; DAVID HENRY; CHARLOTTE GILLOT; ALAN MATHEWSON; LEA DI CIOCCIO; BARBARA CHARLET; PATRICK LEDUC; MAUD VINET; PERRINE BATUDE20092009, vol.97, no.1
A Model of BGA Thermal Vias as an Example of Lumped Parameter Analysis in Thermal Modeling of SiPs and Stacked Die PackagesLUIGI PIETRO MARIA COLOMBO; DAVIDE PALEARI; ALEXEY PETRUSHIN20092009, vol.97, no.1
A Neural Network-Based Prediction Model in Embedded Processes of Gold Wire Bonding Structure for Stacked Die PackageCHIN-HUANG CHANG; YUNG-HSIANG HUNG20092009, vol.97, no.1
Signal Integrity Flow for System-in-Package and Package-on-Package DevicesPAOLO PULICI; GIAN PIETRO VANALLI; MICHELE A. DELLUTRI; DOMENICO GUARNACCIA; FILIPPO LO IACONO; GIOVANNI CAMPARDO; GIANCARLO RIPAMONTI20092009, vol.97, no.1
3-D Technology Assessment: Path-Finding the Technology/Design Sweet-SpotPAUL MARCHAL; BRUNO BOUGARD; GURUPRASAD KATTI; MICHELE STUCCH; WIM DEHAENE; ANTONIS PAPANIKOLAOU; DIEDERIK VERKEST; BART SWINNEN; ERIC BEYNE20092009, vol.97, no.1
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