期刊


ISSN0923-8174
刊名Journal of Electronic Testing
参考译名电子测试杂志：理论与应用
收藏年代2000～2023



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2015, vol.31, no.1 2015, vol.31, no.2 2015, vol.31, no.3 2015, vol.31, no.4 2015, vol.31, no.5/6

题名作者出版年年卷期
UntitledAgrawal, Vishwani D.20152015, vol.31, no.5/6
Performance Degradation Tolerance Analysis and Design for Effective Yield EnhancementHsieh, Tong-Yu; Wang, Chih-Hao; Kuo, Chun-Wei; Huang, Shu-Yu; Chih, Tsung-Liang20152015, vol.31, no.5/6
Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement RangeDavid-Grignot, Stephane; Azais, Florence; Latorre, Laurent; Lefevre, Francois20152015, vol.31, no.5/6
Incipient Fault Diagnostics and Remaining Useful Life Prediction of Analog FiltersXiao, Mingqing; Zhang, Lei; Song, Haifang; Yang, Zhao; Hu, Zewen20152015, vol.31, no.5/6
Defect Level Constrained Optimization of Analog and Radio Frequency Specification TestsSindia, Suraj; Agrawal, Vishwani D.20152015, vol.31, no.5/6
Spot Defect Diagnosis in Analog Nonlinear Circuits with Possible Multiple Operating PointsTadeusiewicz, Michal; Kuczynski, Andrzej; Halgas, Stanislaw20152015, vol.31, no.5/6
A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICsAghaee, Nima; Peng, Zebo; Eles, Petru20152015, vol.31, no.5/6
Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault InjectionGoren, Sezer; Gursoy, Cemil Cem; Yildiz, Abdullah20152015, vol.31, no.5/6
Design and Implementation of an FPGA-Based Data/Timing FormatterChen, Yu-Yi; Huang, Jiun-Lang; Kuo, Terry; Huang, Xuan-Lun20152015, vol.31, no.5/6
Double Node Upsets Hardened Latch CircuitsLi, Yuanqing; Wang, Haibin; Yao, Suying; Yan, Xi; Gao, Zhiyuan; Xu, Jiangtao20152015, vol.31, no.5/6
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