期刊


ISSN0923-8174
刊名Journal of Electronic Testing
参考译名电子测试杂志：理论与应用
收藏年代2000～2023



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2000 2001 2002 2003 2004 2005
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2004, vol.20, no.1 2004, vol.20, no.2 2004, vol.20, no.3 2004, vol.20, no.4 2004, vol.20, no.5 2004, vol.20, no.6

题名作者出版年年卷期
On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data CompressionLEI LI; KRISHNENDU CHAKRABARTY20042004, vol.20, no.6
Area Minimization of Exclusive-OR Intensive Circuits in FPGAsSEOK-BUM KO20042004, vol.20, no.6
Power-Driven Routing-Constrained Scan Chain DesignY. BONHOMME; P. GIRARD; L. GUILLER; C. LANDRAULT; S. PRAVOSSOUDOVITCH20042004, vol.20, no.6
Scan Test Strategy for Asynchronous-Synchronous InterfacesOCTAVIAN PETRE; HANS G. KERKHOFF20042004, vol.20, no.6
A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACsSUNIL RAFEEQUE, K. P.; VINITA VASUDEVAN20042004, vol.20, no.6
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BISTMICHAEL GOESSEL; KRISHNENDU CHAKRABARTY; VITALIJ OCHERETNIJ; ANDREAS LEININGER20042004, vol.20, no.6
Modeling Custom Digital Circuits for TestSOUMITRA BOSE20042004, vol.20, no.6
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault SimulationZAINALABEDIN NAVABI; SHAHRZAD MIRKHANI; MEISAM LAVASANI; FABRIZIO LOMBARDI20042004, vol.20, no.6
Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring FeaturesAMIR RAJABZADEH; SEYED GHASSEM MIREMADI; MIRZAD MOHANDESPOUR20042004, vol.20, no.5
A Two-Level Power-Grid Model for Transient Current Testing EvaluationB. ALORDA; V. CANALS; J. SEGURA20042004, vol.20, no.5
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