期刊


ISSN0923-8174
刊名Journal of Electronic Testing
参考译名电子测试杂志：理论与应用
收藏年代2000～2024



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2024

2012, vol.28, no.1 2012, vol.28, no.2 2012, vol.28, no.3 2012, vol.28, no.4 2012, vol.28, no.5 2012, vol.28, no.6

题名作者出版年年卷期
Optimization Methods for Post-Bond Testing of 3D Stacked ICsBrandon Noia; Krishnendu Chakrabarty; Erik Jan Marinissen20122012, vol.28, no.1
Scheduling Tests for 3D Stacked Chips under Power ConstraintsBreeta SenGupta; Urban Ingelsson; Erik Larsson20122012, vol.28, no.1
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D SystemsVladimir Pasca; Lorena Anghel; Michael Nicolaidis; Mounir Benabdenbi20122012, vol.28, no.1
Test Impact on the Overall Die-to-Wafer 3D Stacked IC CostMottaqiallah Taouil; Said Hamdioui; Kees Beenakker; Erik Jan Marinissen20122012, vol.28, no.1
Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test MethodsYi Lou; Zhuo Yan; Fan Zhang; Paul D. Franzon20122012, vol.28, no.1
Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV DefectsSukeshwar Kannan; Bruce Kim; Byoungchul Ahn20122012, vol.28, no.1
Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated CircuitsBenjamin Backes; Colin McDonough; Larry Smith; Wei Wang; Robert E. Geer20122012, vol.28, no.1
Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device PerformanceValeriy Sukharev; Armen Kteyan; Jun-Ho Choy; Henrik Hovsepyan; Ara Markosian; Ehrenfried Zschech; Rene Huebner20122012, vol.28, no.1
A DfT Architecture for 3D-SICs Based on a Standardizable Die WrapperErik Jan Marinissen; Chun-Chuan Chi; Mario Konijnenburg; Jouke Verbree20122012, vol.28, no.1
On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLsMichael Buttrick; Sandip Kundu20122012, vol.28, no.1



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